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1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B
Y
High-Integration Blocked Architecture One 8 KB Boot Block w Lock Out Two 4 KB Parameter Blocks One 112 KB Main Block 100 000 Erase Program Cycles Per Block Simplified Program and Erase Automated Algorithms via On-Chip Write State Machine (WSM) SRAM-Compatible Write Interface Deep Power-Down Mode 0 05 mA ICC Typical 0 8 mA IPP Typical 12 0V g5% VPP
Y
High-Performance Read 70 75 ns 90 ns 120 ns 150 ns Maximum Access Time 5 0V g10% VCC Hardware Data Protection Feature Erase Write Lockout during Power Transitions Advanced Packaging JEDEC Pinouts 32-Pin PDIP 32-Lead PLCC TSOP ETOX TM II Nonvolatile Flash Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience Extended Temperature Options
Y
Y
Y
Y
Y Y
Y
Y
Y
Intel's 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with features that simplify write and allow block erase These devices aid the system designer by combining the functions of several components into one making boot block flash an innovative alternative to EPROM and EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the 28F001BX's integration of blocked architecture automated electrical reprogramming and standard processor interface The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of 8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and state machine for simplified block erasure and byte reprogramming The 28F001BX-T's block locations provide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel's MCS -186 family 80286 i386 TM i486 TM i860 TM and 80960CA With exactly the same memory segmentation the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory such as Intel's MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is designed to contain secure code which will bring up the system minimally and download code to the other locations of the 28F001BX Intel's 28F001BX employs advanced CMOS circuitry for systems requiring highperformance access speeds low power consumption and immunity to noise Its access time provides no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown mode lowers power consumption to 0 25 mW typical through VCC crucial in laptop computer handheld instrumentation and other low-power applications The RP power control input also provides absolute data protection during system powerup or power loss Manufactured on Intel's ETOX process base the 28F001BX builds on years of EPROM experience to yield the highest levels of quality reliability and cost-effectiveness
NOTE The 28F001BN is equivalent to the 28F001BX
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290406-007
28F001BX-T 28F001BX-B
290406 - 1
Figure 1 28F001BX Block Diagram Table 1 Pin Description Symbol A0 -A16 DQ0 -DQ7 Type INPUT INPUT OUTPUT Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle DATA INPUTS OUTPUTS Inputs data and commands during memory write cycles outputs data during memory Status Register and Identifier read cycles The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled Data is internally latched during a write cycle CHIP ENABLE Activates the device's control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels POWERDOWN Puts the device in deep powerdown mode RP is active low RP high gates normal operation RP e VHH allows programming of the boot block RP also locks out erase or write operations when active low providing data protection during power transitions RP active resets internal automation Exit from deep powerdown sets device to Read Array mode OUTPUT ENABLE Gates the device's outputs through the data buffers during a read cycle OE is active low OE e VHH (pulsed) allows programming of the boot block WRITE ENABLE Controls writes to the Command Register and array blocks WE is active low Addresses and data are latched on the rising edge of the WE pulse ERASE PROGRAM POWER SUPPLY for erasing blocks of the array or programming bytes of each block Note With VPP k VPPL max memory contents cannot be altered DEVICE POWER SUPPLY (5V g10%) GROUND
CE
INPUT
RP
INPUT
OE
INPUT
WE VPP
INPUT
VCC GND 2
28F001BX-T 28F001BX-B
28F010 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 290406 - 2
28F010 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
Figure 2 DIP Pin Configuration
28F010 A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4
28F010 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
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Figure 3 TSOP Lead Configuration
3
28F001BX-T 28F001BX-B
290406 - 4
Figure 4 PLCC Lead Configuration
APPLICATIONS
The 28F001BX flash `boot block' memory augments the non-volatility in-system electrical erasure and reprogrammability of Intel's standard flash memory by offering four separately erasable blocks and integrating a state machine to control erase and program functions The specialized blocking architecture and automated programming of the 28F001BX provide a full-function non-volatile flash memory ideal for a wide range of applications including PC boot BIOS memory minimum-chip embedded program memory and parametric data storage The 28F001BX combines the safety of a hardware-protected 8-KByte boot block with the flexibility of three separately reprogrammable blocks (two 4-KByte parameter blocks and one 112-KByte code block) into one versatile cost-effective flash memory Additionally reprogramming one block does not affect code stored in another block ensuring data integrity
The flexibility of flash memory reduces costs throughout the life cycle of a design During the early stages of a system's life flash memory reduces prototype development and testing time allowing the system designer to modify in-system software electrically versus manual removal of components During production flash memory provides flexible firmware for just-in-time configuration reducing system inventory and eliminating unnecessary handling and less reliable socketed connections Late in the life cycle when software updates or code ``bugs'' are often unpredictable and costly flash memory reduces update costs by allowing the manufacturers to send floppy updates versus a technician Alternatively remote updates over a communication link are possible at speeds up to 9600 baud due to flash memory's fast programming time
4
28F001BX-T 28F001BX-B
Reprogrammable environments such as the personal computer are ideal applications for the 28F001BX The internal state machine provides SRAM-like timings for program and erasure using the Command and Status Registers The blocking scheme allows BIOS update in the main and parameter blocks while still providing recovery code in the boot block in the unlikely event a power failure occurs during an update or where BIOS code is corrupted Parameter blocks also provide convenient configuration storage backing up SRAM and battery configurations EISA systems for example can store hardware configurations in a flash parameter block reducing system SRAM Laptop BIOSs are becoming increasingly complex with the addition of power management software and extended system setup screens BIOS code complexity increases the potential for code updates after the sale but the compactness of laptop designs makes hardware updates very costly Boot block flash memory provides an inexpensive update solution for laptops while reducing laptop obsolescence For portable PCs and hand-held equipment the deep powerdown mode dramatically lowers system power requirements during periods of slow operation or sleep modes The 28F001BX gives the embedded system designer several desired features The internal state machine reduces the size of external code dedicated to the erase and program algorithms as well as freeing the microcontroller or microprocessor to respond to other system requests during program and erasure The four blocks allow logical segmentation of the entire embedded software the 8-KByte block for the boot code the 112-KByte block for the main program code and the two 4-KByte blocks for updatable parametric data storage diagnostic messages and data or extensions of either the boot code or program code The boot block is hardware protected against unauthorized write or erase of its vital code in the field Further the powerdown mode also locks out erase or write operations providing absolute data protection during system powerup or power loss This hardware protection provides obvious advantages for safety related applications such as transportation military and medical The 28F001BX is well suited for minimum-chip embedded applications ranging from communications to automotive
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Figure 5 28F001BX-T in a 80C188 System
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Figure 6 28F001BX-B in a 80C51 System
5
28F001BX-T 28F001BX-B
PRINCIPLES OF OPERATION
The 28F001BX introduces on-chip write automation to manage write and erase functions The write state machine allows for 100% TTL-level control inputs fixed power supplies during erasure and programming minimal processor overhead with RAM-like write timings and maximum EPROM compatiblity After initial device powerup or after return from deep powerdown mode (see Bus Operations) the 28F001BX functions as a read-only memory Manipulation of external memory-control pins yield standard EPROM read standby output disable or Intelligent Identifier operations Both Status Register and Intelligent Identifiers can be accessed through the Command Register when VPP e VPPL This same subset of operations is also available when high voltage is applied to the VPP pin In addition high voltage on VPP enables successful erasure and programming of the device All functions associated with altering memory contents program erase status and inteligent Identifier are accessed via the Command Register and verified through the Status Register Commands are written using standard microprocessor write timings Register contents serve as input to the WSM which controls the erase and programming circuitry Write cycles also internally latch addresses and data needed for programming or erase operations With the appropriate command written to the register standard microprocessor read timings output array data access the intelligent identifier codes or output program and erase status for verification Interface software to initiate and poll progress of internal program and erase can be stored in any of the 28F001BX blocks This code is copied to and executed from system RAM during actual flash memory update After successful completion of program and or erase code execution out of the 28F001BX is again possible via the Read Array command Erase suspend resume capability allows system software to suspend block erase and read data execute code from any other block
Data Protection
Depending on the application the system designer may choose to make the VPP power supply switchable (available only when memory updates are required) or hardwired to VPPH When VPP e VPPL memory contents cannot be altered The 28F001BX Command Register architecture provides protection from unwanted program or erase operations even when high voltage is applied to VPP Additionally all functions are disabled whenever VCC is below the write lockout voltage VLKO or when RP is at VIL The 28F001BX accommodates either design practice and encourages optimization of the processormemory interface The two-step program erase write sequence to the Command Register provides additional software write protection
1FFFF 8-KByte BOOT BLOCK 1E000 1DFFF 1D000 1CFFF 1C000 1BFFF 4-KByte PARAMETER BLOCK 4-KByte PARAMETER BLOCK
112-KByte MAIN BLOCK
00000
Figure 7 28F001BX-T Memory Map
1FFFF
Command Register and Write Automation
An on-chip state machine controls block erase and byte program freeing the system processor for other tasks After receiving the erase setup and erase confirm commands the state machine controls block pre-conditioning and erase returning progress via the Status Register Programming is similarly controlled after destination address and expected data are supplied The program algorithm of past Intel Flash Memories is now regulated by the state machine including program pulse repetition where required and internal verification and margining of data 6
04000 03FFF 03000 02FFF 02000 01FFF
112-KByte MAIN BLOCK
4-KByte PARAMETER BLOCK 4-KByte PARAMETER BLOCK
8-KByte BOOT BLOCK 00000
Figure 8 28F001BX-B Memory Map
28F001BX-T 28F001BX-B
BUS OPERATION
Flash memory reads erases and writes in-system via the local CPU All bus cycles to or from the flash memory conform to standard microprocessor bus cycles
Standby
CE at a logic-high level (VIH) places the 28F001BX in standby mode Standby operation disables much of the 28F001BX's circuitry and substantially reduces device power consumption The outputs (DQ0 - DQ7) are placed in a high-impedance state independent of the status of OE If the 28F001BX is deselected during erase or program the device will continue functioning and consuming normal active power until the operation is completed
Read
The 28F001BX has three read modes The memory can be read from any of its blocks and information can be read from the Intelligent Identifier or the Status Register VPP can be at either VPPL or VPPH The first task is to write the appropriate read mode command to the Command Register (array Intelligent Identifier or Status Register) The 28F001BX automatically resets to Read Array mode upon initial device powerup or after exit from deep powerdown The 28F001BX has four control pins two of which must be logically active to obtain data at the outputs Chip Enable (CE ) is the device selection control and when active enables the selected memory device Output Enable (OE ) is the data input output (DQ0 -DQ7) direction control and when active drives data from the selected memory onto the I O bus RP and WE must also be at VIH Figure 12 illustrates read bus cycle waveforms
Deep Power-Down
The 28F001BX offers a 0 25 mW VCC power-down feature entered when RP is at VIL During read modes RP low deselects the memory places output drivers in a high-impedance state and turns off all internal circuits The 28F001BX requires time tPHQV (see AC Characteristics-Read Only Operations) after return from power-down until initial memory access outputs are valid After this wakeup interval normal operation is restored The Command Register is reset to Read Array and the Status Register is cleared to value 80H upon return to normal operation During erase or program modes RP low will abort either operation Memory contents of the block being altered are no longer valid as the data will be partially programmed or erased Time tPHWL after RP goes to logic-high (VIH) is required before another command can be written
Output Disable
With OE at a logic-high level (VIH) the device outputs are disabled Output pins (DQ0 -DQ7) are placed in a high-impedance state
Table 2 28F001BX Bus Operations Mode Read Output Disable Standby Deep Power Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes 123 2 2 2 234 2345 2678 RP VIH VIH VIH VIL VIH VIH VIH CE VIL VIL VIH X VIL VIL VIL OE VIL VIH X X VIL VIL VIH WE VIH VIH X X VIH VIH VIL A9 X X X X VID VID X A0 X X X X VIL VIH X VPP X X X X X X X DQ0-7 DOUT High Z High Z High Z 89H 94H 95H DIN
NOTES 1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not programmed or erased 2 X can be VIL or VIH for control pins and addresses and VPPL or VPPH for VPP 3 See DC Characteristics for VPPL VPPH VHH and VID voltages 4 Manufacturer and device codes may also be accessed via a Command Register write sequence Refer to Table 3 A1 -A8 A10 - A16 e VIL 5 Device ID e 94H for the 28F001BX-T and 95H for the 28F001BX-B 6 Command writes involving block erase or byte program are successfully executed only when VPP e VPPH 7 Refer to Table 3 for valid DIN during a write operation 8 Program or erase the boot block by holding RP at VHH or toggling OE to VHH See AC Waveforms for program erase operations
7
28F001BX-T 28F001BX-B
The use of RP during system reset is important with automated write erase devices When the system comes out of reset it expects to read from the flash memory Automated flash memories provide status information when accessed during write erase modes If a CPU reset occurs with no flash memory reset proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data Intel's Flash Memories allow proper CPU initialization following a system reset through the use of the RP input In this application RP is controlled by the same RESET signal that resets the system CPU Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased The Program Setup Command requires both appropriate command data and the address of the location to be programmed while the Program command consists of the data to be written and the address of the location to be programmed The Command Register is written by bringing WE to a logic-low level (VIL) while CE is low Addresses and data are latched on the rising edge of WE Standard microprocessor write timings are used Refer to AC Write Characteristics and the AC Waveform for Write Operations Figure 13 for specific timing parameters
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code 89H and the device code 94H for the 28F001BX-T and 95H for the 28F001BX-B Programming equipment or the system CPU can then automatically match the device with its proper erase and programming algorithms PROGRAMMING EQUIPMENT CE and OE at a logic low level (VIL) with A9 at high voltage VID (see DC Characteristics) activates this operation Data read from locations 00000H and 00001H represent the manufacturer's code and the device code respectively IN-SYSTEM PROGRAMMING The manufacturer- and device-codes can also be read via the Command Register Following a write of 90H to the Command Register a read from address location 00000H outputs the manufacturer code (89H) A read from address 00001H outputs the device code (94H for the 28F001BX-T and 95H for the 28F001BX-B) It is not necessary to have high voltage applied to VPP to read the Intelligent Identifiers from the Command Register
COMMAND DEFINITIONS
When VPPL is applied to the VPP pin read operations from the Status Register intelligent identifiers or array blocks are enabled Placing VPPH on VPP enables successful program and erase operations as well Device operations are selected by writing specific commands into the Command Register Table 3 defines these 28F001BX commands
Read Array Command
Upon initial device powerup and after exit from deep-powerdown mode the 28F001BX defaults to Read Array mode This operation is also initiated by writing FFH into the Command Register Microprocessor read cycles retrieve array data The device remains enabled for reads until the Command Register contents are altered Once the internal write state machine has started an erase or program operation the device will not recognize the Read Array command until the WSM has completed its operation The Read Array command is functional when VPP e VPPL or VPPH
Write
Writes to the Command Register allow read of device data and Intelligent Identifiers They also control inspection and clearing of the Status Register Additionally when VPP e VPPH the Command Register controls device erasure and programming The contents of the register serve as input to the internal state machine The Command Register itself does not occupy an addressable memory location The register is a latch used to store the command and address and data information needed to execute the command Erase
Intelligent Identifier Command for In-System Programming
The 28F001BX contains an Intelligent Identifier operation to supplement traditional PROM-programming methodology The operation is initiated by writing 90H into the Command Register Following the command write a read cycle from address 00000H retrieves the manufacturer code of 89H A read cycle from address 00001H returns the device code of 94H (28F001BX-T) or 95H (28F001BX-B) To terminate the operation it is necessary to write another valid command into the register Like the Read Array command the Intelligent Identifier command is functional when VPP e VPPL or VPPH
8
28F001BX-T 28F001BX-B
Table 3 28F001BX Command Definitions Command Read Array Reset Intelligent Identifier Read Status Register Clear Status Register Erase Setup Erase Confirm Erase Suspend Erase Resume Program Setup Program Bus First Bus Cycle Second Bus Cycle Cycles Notes Req'd Operation Address Data Operation Address Data 1 3 2 1 2 2 2 23 2 1 234 3 Write Write Write Write Write Write Write X X X X BA X PA FFH 90H 70H 50H 20H B0H 40H Write Write Write BA X PA D0H D0H PD Read Read IA X IID SRD
NOTES 1 Bus operations are defined in Table 2 2 IA e Identifier Address 00H for manufacturer code 01H for device code BA e Address within the block being erased PA e Address of memory location to be programmed 3 SRD e Data read from Status Register See Table 4 for a description of the Status Register bits PD e Data to be programmed at location PA Data is latched on the rising edge of WE IID e Data read from Intelligent Identifiers 4 Following the Intelligent Identifier command two read operations access manufacture and device codes 5 Commands other than those shown above are reserved by Intel for future device implementations and should not be used
Read Status Register Command
The 28F001BX contains a Status Register which may be read to determine when a program or erase operation is complete and whether that operation completed successfully The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command Register After writing this command all subsequent read operations output data from the Status Register until another valid command is written to the Command Register The contents of the Status Register are latched on the falling edge of OE or CE whichever occurs last in the read cycle OE or CE must be toggled to VIH before further reads to update the Status Register latch The Read Status Register command functions when VPP e VPPL or VPPH
reset by the Clear Status Register command These bits indicate various failure conditions (see Table 4) By allowing system software to control the resetting of these bits several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence) The Status Register may then be polled to determine if an error occurred during that series This adds flexibility to the way the device may be used Additionally the VPP Status bit (SR 3) when set to ``1'' MUST be reset by system software before further byte programs or block erases are attempted To clear the Status Register the Clear Status Register command (50H) is written to the Command Register The Clear Status Register command is functional when VPP e VPPL or VPPH
Clear Status Register Command
The Erase Status and Program Status bits are set to ``1'' by the Write State Machine and can only be
9
28F001BX-T 28F001BX-B
Table 4 28F001BX Status Register Definitions WSMS 7 ESS 6 ES 5 PS 4 VPPS 3 R 2 R 1 R 0
SR 7 e WRITE STATE MACHINE STATUS 1 e Ready 0 e Busy SR 6 e ERASE SUSPEND STATUS 1 e Erase Suspended 0 e Erase In Progress Completed SR 5 e ERASE STATUS 1 e Error in Block Erasure 0 e Successful Block Erase SR 4 e PROGRAM STATUS 1 e Error in Byte Program 0 e Successful Byte Program SR 3 e VPP STATUS 1 e VPP Low Detect Operation Abort 0 e VPP OK SR 2 - SR 0 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register
NOTES The Write State Machine Status Bit must first be checked to determine program or erase completion before the Program or Erase Status bits are checked for success If the Program AND Erase Status bits are set to ``1s'' during an erase attempt an improper command sequence was entered Attempt the operation again If VPP low status is detected the Status Register must be cleared before another program or erase operation is attempted The VPP Status bit unlike an A D converter does not provide continuous indication of VPP level The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP has not been switched on The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH
Erase Setup Erase Confirm Commands
Erase is executed one block at a time initiated by a two-cycle command sequence An Erase Setup command (20H) is first written to the Command Register followed by the Erase Confirm command (D0H) These commands require both appropriate command data and an address within the block to be erased Block preconditioning erase and verify are all handled internally by the Write State Machine invisible to the system After receiving the two-command erase sequence the 28F001BX automatically outputs Status Register data when read (see Figure 10 Block Erase Flowchart) The CPU can detect the completion of the erase event by checking the WSM Status bit of the Status Register (SR 7) When the Status Register indicates that erase is complete the Erase Status bit should be checked If erase error is detected the Status Register should be cleared The Command Register remains in Read Status Register Mode until further commands are issued to it This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased Also block erasure can only occur when VPP e VPPH In the absence of this high voltage memory contents are protected against erasure If block erase is attempted while VPP e VPPL 10
the VPP Status bit will be set to ``1'' Erase attempts while VPPL k VPP k VPPH produce spurious results and should not be attempted
Erase Suspend Erase Resume Commands
The Erase Suspend Command allows erase sequence interruption in order to read data from another block of memory Once the erase sequence is started writing the Erase Suspend command (B0H) to the Command Register requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm The 28F001BX continues to output Status Register data when read after the Erase Suspend command is written to it Polling the WSM Status and Erase Suspend Status bits will determine when the erase operation has been suspended (both will be set to ``1s'') At this point a Read Array command can be written to the Command Register to read data from blocks other than that which is suspended The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H) at which time the WSM will continue with the erase sequence The Erase Suspend Status and WSM Status bits of the Status Register will be cleared After the Erase Resume command is written to it the 28F001BX automatically outputs Status Register data when read (see Figure 11 Erase Suspend Resume Flowchart)
28F001BX-T 28F001BX-B
The 28F001BX-B and 28F001BX-T are capable of 100 000 program erase cycles on each parameter block main block and boot block
Program Setup Program Commands
Programming is executed by a two-write sequence The program Setup command (40H) is written to the Command Register followed by a second write specifying the address and data (latched on the rising edge of WE ) to be programmed The WSM then takes over controlling the program and verify algorithms internally After the two-command program sequence is written to it the 28F001BX automatically outputs Status Register data when read (see Figure 9 Byte Program Flowchart) The CPU can detect the completion of the program event by analyzing the WSM Status bit of the Status Register Only the Read Status Register command is valid while programming is active When the Status Register indicates that programming is complete the Program Status bit should be checked If program error is detected the Status Register should be cleared The internal WSM verify only detects errors for ``1s'' that do not successfully program to ``0s'' The Command Register remains in Read Status Register mode until further commands are issued to it If byte program is attempted while VPP e VPPL the VPP Status bit will be set to ``1'' Program attempts while VPPL k VPP k VPPH produce spurious results and should not be attempted
ON-CHIP PROGRAMMING ALGORITHM
The 28F001BX integrates the Quick Pulse programming algorithm of prior Intel Flash Memory devices on-chip using the Command Register Status Register and Write State Machine (WSM) On-chip integration dramatically simplifies system software and provides processor-like interface timings to the Command and Status Registers WSM operation internal program verify and VPP high voltage presence are monitored and reported via appropriate Status Register bits Figure 9 shows a system software flowchart for device programming The entire sequence is performed with VPP at VPPH Program abort occurs when RP transitions to VIL or VPP drops to VPPL Although the WSM is halted byte data is partially programmed at the location where programming was aborted Block erasure or a repeat of byte programming will initialize this data to a known value
ON-CHIP ERASE ALGORITHM EXTENDED ERASE PROGRAM CYCLING
EEPROM cycling failures have always concerned users The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions To combat this some suppliers have implemented redundancy schemes reducing cycling failures to insignificant levels However redundancy requires that cell size be doubled an expensive solution Intel has designed extended cycling capability into its ETOX flash memory technology Resulting improvements in cycling reliability come without increasing memory cell size or complexity First an advanced tunnel oxide increases the charge carrying ability ten-fold Second the oxide area per cell subjected to the tunneling electrical field is onetenth that of common EEPROMs minimizing the probability of oxide defects in the region Finally the peak electric field during erasure is approximately 2 Mv cm lower than EEPROM The lower electric field greatly reduces oxide stress and the probability of failure As above the Quick Erase algorithm of prior Intel Flash Memory devices is now implemented internally including all preconditioning of block data WSM operation erase success and VPP high voltage presence are monitored and reported through the Status Register Additionally if a command other than Erase Confirm is written to the device after Erase Setup has been written both the Erase Status and Program Status bits will be set to ``1'' When issuing the Erase Setup and Erase Confirm commands they should be written to an address within the address range of the block to be erased Figure 10 shows a system software flowchart for block erase Erase typically takes 1 - 4 seconds per block The Erase Suspend Erase Resume command sequence allows interrupt of this erase operation to read data from a block other than that in which erase is being performed A system software flowchart is shown in Figure 11 The entire sequence is performed with VPP at VPPH Abort occurs when RP transitions to VIL or VPP falls to VPPL while erase is in progress Block data is partially erased by this operation and a repeat of erase is required to obtain a fully erased block
11
28F001BX-T 28F001BX-B
tion being attempted and indicating boot block lock Program erase attempts while VIH k RP k VHH produce spurious results and should not be attempted In-System Operation For on-board programming the RP pin is the most convenient means of altering the boot block Before issuing Program or Erase confirms commands RP must transition to VHH Hold RP at this high voltage throughout the program or erase interval (until after Status Register confirm of successful completion) At this time it can return to VIH or VIL
BOOT BLOCK PROGRAM AND ERASE
The boot block is intended to contain secure code which will minimally bring up a system and control programming and erase of other blocks of the device if needed Therefore additional ``lockout'' protection is provided to guarantee data integrity Boot block program and erase operations are enabled through high voltage VHH on either RP or OE and the normal program and erase command sequences are used Reference the AC Waveforms for Program Erase If boot block program or erase is attempted while RP is at VIH either the Program Status or Erase Status bit will be set to ``1'' reflective of the opera-
Bus Operation Write
Command Program Setup Program
Comments Data e 40H Address e Byte to be Programmed Data to be programmed Address e Byte to be Programmed Status Register Data Toggle OE or CE to update Status Register Check SR 7 1 e Ready 0 e Busy
Write
Read Standby
Repeat for subsequent bytes Full status check can be done after each byte or after a sequence of bytes Write FFH after the last byte programming operation to reset the device to Read Array Mode Bus Operation
Command
Comments
Standby
Check SR 3 1 e VPP Low Detect
Standby
Check SR 4 1 e Byte Program Error
SR 3 MUST be cleared if set during a program attempt before further attempts are allowed by the Write State Machine
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SR 4 is only cleared by the Clear Status Register Command in cases where multiple bytes are programmed before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery
Figure 9 28F001BX Byte Programming Flowchart 12
28F001BX-T 28F001BX-B
Bus Operation
Command
Comments
Write
Erase Setup Erase
Data e 20H Address e Within Block to be erased Data e D0H Address e Within Block to be erased Status Register Data Toggle OE or CE to update Status Register Check SR 7 1 e Ready 0 e Busy
Write
Read
Standby
Repeat for subsequent blocks Full status check can be done after each block or after a sequence of blocks Write FFH after the last block erase operation to reset the device to Read Array Mode
Bus Operation
Command
Comments
Standby
Check SR 3 1 e VPP Low Detect
Standby
Check SR 4 5 Both 1 e Command Sequence Error
Standby
Check SR 5 1 e Block Erase Error
SR 3 MUST be cleared if set during an erase attempt before further attempts are allowed by the Write State Machine
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SR 5 is only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery
Figure 10 28F001BX Block Erase Flowchart
13
28F001BX-T 28F001BX-B
Bus Operation
Command
Comments
Write
Erase Suspend Erase Status Register
Data e B0H
Write
Data e 70H
Standby Read
Read Status Register Check SR 7 1 e Ready 0 e Busy Toggle OE or CE to Update Status Register
Standby
Check SR 6 1 e Suspended
Write
Read Array
Data e FFH
Read
Read array data from block other than that being erased Erase Resume Data e D0H
Write
290406 - 9
Figure 11 28F001BX Erase Suspend Resume Flowchart Programming Equipment For PROM programming equipment that cannot bring RP to high voltage OE provides an alternate boot block access mechanism OE must transition to VHH a minimum of 480 ns before the initial program erase setup command and held at VHH at least 480 ns after program or erase confirm commands are issued to the device After this interval OE can return to normal TTL levels date multiple memory connections Three-line control provides for a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs an address decoder should enable CE while OE should be connected to all memory devices and the system's READ control line This assures that only selected memory devices have active outputs while deselected memory devices are in Standby Mode RP should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions POWERGOOD should also toggle during system reset
DESIGN CONSIDERATIONS Three-Line Output Control
Flash memories are often used in larger memory arrays Intel provides three control inputs to accommo14
28F001BX-T 28F001BX-B
After program or erase is complete even after VPP transitions down to VPPL the Command Register must be reset to read array mode via the Read Array command if access to the memory array is desired
Power Supply Decoupling
Flash memory power switching characteristics require careful device coupling System designers are interested in 3 supply current issues standby current levels (ISB) active current levels (ICC) and transient peaks producted by falling and rising edges of CE Transient current magnitudes depend on the device outputs' capacitive and inductive loading Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks Each device should have a 0 1 mF ceramic capacitor connected between its VCC and GND and between its VPP and GND These high frequency low inherent-inductance capacitors should be placed as close as possible to the device Additionally for every 8 devices a 4 7 mF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND The bulk capacitor will overcome voltage slumps caused by PC board trace inductances
Power Up Down Protection
The 28F001BX is designed to offer protection against accidental erasure or programming during power transitions Upon power-up the 28F001BX is indifferent as to which power supply VPP or VCC powers up first Power supply sequencing is not required Internal circuitry in the 28F001BX ensures that the Command Register is reset to Read Array mode on power up A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active Since both WE and CE must be low for a command write driving either to VIH will inhibit writes The Command Register architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences Finally the device is disabled until RP is brought to VIH regardless of the state of its control inputs This provides an additional level of protection
VPP Trace on Printed Circuit Boards
Programming flash memories while they reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace The VPP pin supplies the memory cell current for programming Use similar trace widths and layout considerations given to the VCC power bus Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots
28F001BX Power Dissipation
When designing portable systems designers must consider battery power consumption not only during device operation but also for data retention during system idle time Flash nonvolatility increases usable battery life because the 28F001BX does not consume any power to retain code or data when the system is off In addition the 28F001BX's Deep-Powerdown mode ensures extremely low power dissipation even when system power is applied For example laptop and other PC applications after copying BIOS to DRAM can lower RP to VIL producing negligible power consumption If access to the boot code is again the part needed as in case of a system RESET can again be accessed following the tPHAV wakeup cycle required after RP is first raised back to VIH The first address presented to the device while in powerdown requires time tPHAV after RP transitions high before outputs are valid Further accesses follow normal timing See AC Characteristics Read-Only Operations and Figure 12 for more information
VCC VPP RP Transitions and the Command Status Registers
Programming and erase completion are not guaranteed if VPP drops below VPPH If the VPP Status bit of the Status Register (SR 3) is set to ``1'' a Clear Status Register command MUST be issued before further program erase attempts are allowed by the WSM Otherwise the Program (SR 4) or Erase (SR 5) Status bits of the Status Register will be set to ``1'' if error is detected RP transitions to VIL during program and erase also abort the operations Data is partially altered in either case and the command sequence must be repeated after normal operation is restored Device poweroff or RP transitions to VIL clear the Status Register to initial value 80H The Command Register latches commands as issued by system software and is not altered by VPP or CE transitions or WSM actions Its state upon powerup after exit from Deep-Powerdown or after VCC transitions below VLKO is FFH or Read Array Mode
15
28F001BX-T 28F001BX-B
ABSOLUTE MAXIMUM RATINGS
Operating Temperature During Read During Erase Program Operating Temperature During Read During Erase Program Temperature under Bias Temperature under Bias Storage Temperature Voltage on Any Pin (except A9 RP OE with Respect to GND 0 C to 70 C(1) 0 C to 70 C(1)
b 40 C to a 85 C(2) b 40 C to a 85 C(2) b 10 C to 80 C(1) b 20 C to a 90 C(2) b 65 C to 125 C
NOTICE This is a production data sheet The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
VCC and VPP) b 2 0V to 7 0V(3)
b 2 0V to 13 5V(3 4)
Voltage on A9 RP and OE with Respect to GND VPP Program Voltage with Respect to GND During Erase Program VCC Supply Voltage with Respect to GND Output Short Circuit Current
b 2 0V to 14 0V(3 4) b 2 0V to 7 0V(3)
100 mA(5)
OPERATING CONDITIONS
Symbol TA TA VCC Parameter Operating Temperature(1) Operating Temperature(2) Supply Voltage Min 0
b 40
Max 70 85 5 50
Unit C C V
4 50
NOTES 1 Operating temperature is for commercial product defined by this specification 2 Operating temperature is for extended temperature product defined by this specification 3 Minimum DC voltage is b0 5V on input output pins During transitions this level may undershoot to b2 0V for periods k 20 ns Maximum DC voltage on input output pins is VCC a 0 5V which during transitions may overshoot to VCC a 2 0V for periods k20 ns 4 Maximum DC voltage on A9 or VPP may overshoot to a 14 0V for periods k20 ns 5 Output shorted for no more than one second No more than one output shorted at a time
DC CHARACTERISTICS
VCC e 5 0V g10% TA e 0 C to a 70 C Symbol IIL ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes Min 1 1 12 30 ICCD 16 VCC Deep Power-Down Current 1 0 05 Typ Max
g1 0
Unit mA mA mA mA mA
Test Conditions VCC e VCC Max VIN e VCC or GND VCC e VCC Max VOUT e VCC or GND VCC e VCC Max CE e RP e VIH VCC e VCC Max CE e RP e VCC g0 2V RP
e GND g0 2V
g10
20 100 10
28F001BX-T 28F001BX-B
DC CHARACTERISTICS (Continued)
VCC e 5 0V g10% TA e 0 C to a 70 C Symbol ICCR ICCP ICCE ICCES IPPS IPPD IPPP IPPE IPPES IID VIL VIH VOL VOH VID VPPL VPPH VLKO VHH Parameter VCC Read Current VCC Programming Current VCC Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current VPP Programming Current VPP Erase Current VPP Erase Suspend Current A9 Intelligent Identifier Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Intelligent Identifier Voltage VPP during Normal Operations VPP during Prog Erase Operations VCC Erase Write Lock Voltage RP OE Unlock Voltage 3 24 11 5 00 11 4 12 0 25 11 4 12 6 13 0 65 12 6 Notes Min Typ 1 1 1 12 1 13 5 6 5
g1
Max 30 20 20 10
g10
Unit
Test Conditions
mA VCC e VCC Max CE e VIL f e 8 MHz IOUT e 0 mA mA Programming in Progress mA Erase in Progress mA Erase Suspended CE e VIH mA VPP s VCC mA VPP l VCC mA RP
e GND g0 2V
90 1 1 1 1 1
b0 5
200 10 30 30 300 500 08 VCC a 0 5 0 45
0 80 6 6 90 90
mA VPP e VPPH Programming in Progress mA VPP e VPPH Erase in Progress mA VPP e VPPH Erase Suspended mA A9 e VID V V V V V V V V V Boot Block Prog Erase VCC e VCC Min IOL e 5 8 mA VCC e VCC Min IOH e 2 5 mA
20
NOTES 1 All currents are in RMS unless otherwise noted Typical values at VCC e 5 0V VPP e 12 0V TA e 25 C These currents are valid for all product versions (packages and speeds) 2 ICCES is specified with the device deselected If the 28F001BX is read while in Erase Suspend mode current draw is the sum of ICCES and ICCR 3 Erase Programs are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL
17
28F001BX-T 28F001BX-B
DC CHARACTERISTICS
VCC e 5 0V g10% TA e b 40 C to a 85 C Symbol IIL ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 12 30 ICCD ICCR ICCP ICCE ICCES IPPS IPPD IPPP IPPE IPPES IID VIL VIH VOL VOH1 VOH2 VCC Deep Power-Down Current VCC Read Current VCC Programming Current VCC Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current VPP Programming Current VPP Erase Current VPP Erase Suspend Current A9 Intelligent Identifier Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) 24 0 85 VCC VCC b 0 4 VID VPPL VPPH VLKO VHH 18 A9 Intelligent Identifier Voltage VPP during Normal Operations VPP during Prog Erase Operations VCC Erase Write Lock Voltage RP OE Unlock Voltage 3 11 5 00 11 4 25 11 4 12 6 12 0 13 0 65 12 6 V V V V V Boot Block Prog Erase 1 1 1 1 12 1 0 05 13 5 6 5
g1
Min
Typ
Max
g1 0
Unit
Test Conditions
mA VCC e VCC Max VIN e VCC or GND mA VCC e VCC Max VOUT e VCC or GND mA VCC e VCC Max CE e RP e VIH mA VCC e VCC Max CE e RP e VCC g0 2V mA RP
e GND g0 2V
g10
20 150 20 35 20 20 10
g15
mA VCC e VCC Max CE e VIL f e 8 MHz IOUT e 0 mA mA Programming in Progress mA Erase in Progress mA Erase Suspended CE e VIH mA VPP s VCC mA VPP l VCC mA RP
e GND g0 2V
90 1 1 1 1 1
b0 5
400 10 30 30 400 500 08
0 80 6 6 90 90
mA VPP e VPPH Programming in Progress mA VPP e VPPH Erase in Progress mA VPP e VPPH Erase Suspended mA A9 e VID V
20
VCC a 0 5 V 0 45 V VCC e VCC Min IOL e 5 8 mA V VCC e VCC Min IOH e 2 5 mA V VCC e VCC Min IOH e b 2 5 mA VCC e VCC Min IOH e b 100 mA
28F001BX-T 28F001BX-B
NOTES 1 All currents are in RMS unless otherwise noted Typical values at VCC e 5 0V VPP e 12 0V TA e 25 C These currents are valid for all product versions (packages and speeds) 2 ICCES is specified with the device deselected If the 28F001BX is read while in Erase Suspend mode current draw is the sum of ICCES and ICCR 3 Erase Programs are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL
CAPACITANCE(1)
Symbol CIN COUT
TA e 25 C f e 1 MHz Max 8 12 Unit pF pF Conditions VIN e 0V VOUT e 0V
Parameter Input Capacitance Output Capacitance
NOTE 1 Sampled not 100% tested
AC INPUT OUTPUT REFERENCE WAVEFORM
290406 - 10
A C test inputs are driven at VOH (2 4 VTTL) for a Logic ``1'' and VOL (0 45 VTTL) for a Logic ``0'' Input timing begins at VIH (2 0 VTTL) and VIL (0 8 VTTL) Output timing ends at VIH and VIL Input rise and fall times (10% to 90%) k 10 ns
STANDARD TEST CONFIGURATION AC TESTING LOAD CIRCUIT
HIGH SPEED TEST CONFIGURATION AC TESTING LOAD CIRCUIT
290406 - 11
CL e 100 pF CL Includes Jig Capacitance RL e 3 3 kX
290406 - 23
CL e 30 pF CL Includes Jig Capacitance RL e 3 3 kX
19
28F001BX-T 28F001BX-B
AC CHARACTERISTICS
Read-Only Operations(1)
28F001BX-70 VCC e 5V VCC e 5V
g10%
28F001BX-90 VCC e 5V
g10%
Symbol
Parameter
Notes Min
g5%
Units
30 pF Max
100 pF Min 75 70 75 75 600 30 0 55 55 0 30 30 0 0 0 0 Max
100 pF Min 90 90 90 600 35 Max ns ns ns ns ns ns 35 ns ns 30 ns ns
tAVAV tELQV
tRC Read Cycle Time tCE CE to Output Delay to Output Delay to Output Delay to Output in Low Z to Output in High Z to Output in Low Z to Output in High Z 2 3 3 3 3 3 2
70
tAVQV tACC Address to Output Delay tPHQV tPWH RP tGLQV tOE OE tELQX tLZ CE tEHQZ tHZ CE tGLQX tOLZ OE tGHQZ tDF OE
70 600 27 0
0
tOH Output Hold from Address CE or OE Change Whichever Occurs First
0
NOTES 1 See AC Input Output Reference Waveform for timing measurements 2 OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE 3 Sampled but not 100% tested 4 See High Speed Test Configuration 5 See Standard Test Configuration
20
28F001BX-T 28F001BX-B
AC CHARACTERISTICS
Read-Only Operations(1)
E28F001BX-120 N28F001BX-120 P28F001BX-120 Min 120 120 3 120 600 3 4 4 4 4 4 0 0 30 0 0 55 0 30 50 0 55 Max E28F001BX-150 TE28F001BX-150 N28F001BX-150 TN28F001BX-150 P28F001BX-150 Min 150 150 150 600 55 Max ns ns ns ns ns ns ns ns ns ns
Versions(2)
VCC g10%
Unit
Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tRC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH
Parameter Read Cycle Time Address to Output Delay CE RP OE CE CE OE OE to Output Delay High to Output Delay to Output Delay to Output Low Z High to Output High Z to Output Low Z High to Output High Z
Notes
Output Hold from Addresses CE or OE Change Whichever is First
NOTES 1 See AC Input Output Reference Waveform for timing measurements 2 Model Number Prefixes E e TSOP (Standard Pinout) N e PLCC P e PDIP T e Extended Temperature Refer to standard test configuration 3 OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE 4 Sampled not 100% tested
21
28F001BX-T 28F001BX-B
Figure 12 AC Waveform for Read Operations 22
290406- 12
28F001BX-T 28F001BX-B
AC CHARACTERISTICS
Write Erase Program Operations(1 9)
28F001BX-70 VCC e 5V VCC e 5V 28F001BX-90 VCC e 5V
g10%(11)
Symbol
Parameter
Notes
g5%(10)
g10%(11)
Units
30 pF Min tAVAV tPHWL tELWL tWLWH tWC tPS tCS tWP Write Cycle Time RP High Recovery to WE Going Low CE WE Setup to WE Pulse Width Going 2 2 3 4 Going Low 2 70 480 10 35 100 100 35 35 10 10 10 35 567 567 567 567 15 13 13 30 0 26 27 2 0 0 100 Max
100 pF Min 75 480 10 40 100 100 40 40 10 10 10 35 15 13 13 30 0 0 0 100 Max
100 pF Min 90 480 10 40 100 100 40 40 10 10 10 35 15 13 13 30 0 0 0 100 Max ns ns ns ns ns ns ns ns ns ns ns ns ms sec sec sec ms ns ns ns
tPHHWH tPHS RP VHH Setup to WE High tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tWHGL tQVVL tQVPH tPHBR tVPS VPP Setup to WE tAS tDS tDH tAH tCH Address Setup to WE High Data Setup to WE Data Hold from WE CE Hold from WE
Going High Going
Going High High High High
Address Hold from WE Pulse Width High
tWPH WE
Duration of Programming Operation Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) Write Recovery before Read tVPH VPP Hold from Valid SRD tPHH RP VHH Hold from Valid SRD Boot-Block Relock Delay
NOTES 1 Read timing characteristics during erase and program operations are the same as during read-only operations Refer to AC Characteristics for Read-Only Operations 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte programming or block erasure 4 Refer to Table 3 for valid DIN for byte programming or block erasure 5 The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel Flash Memory including byte program and verify (programming) and block precondition precondition verify erase and erase verify (erasing) 6 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of program erase success (SR 3 4 5 e 0) 7 For boot block programming and erasure RP should be held at VHH until determination of program erase success (SR 3 4 5 e 0) 8 Alternate boot block access method 9 Erase Program Cycles on extended temperature products is 10 000 cycles 10 See high speed test configuration 11 See standard test configuration
23
28F001BX-T 28F001BX-B
AC CHARACTERISTICS
Versions Symbol tAVAV tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tWHGL tQVVL tQVPH tPHBR tVPH tPHH tWC tPS tCS tWP tVPS tAS tDS tDH tAH tCH
Write Erase Program Operations(1 9)
VCC g10%(10) Parameter Notes 28F001BX-120 Min 120 Going Low 2 480 10 50 Going High 2 2 3 4 100 100 50 50 10 10 10 50 567 567 567 567 15 13 13 30 0 26 27 2 0 0 100 Max 28F001BX-150 Min 150 480 10 50 100 100 50 50 10 10 10 50 15 13 13 30 0 0 0 100 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ms sec sec sec ms ns ns ns
Write Cycle Time RP CE WE RP High Recovery to WE Setup to WE Pulse Width VHH Setup to WE
Going Low
tPHHWH tPHS
VPP Setup to WE Data Setup to WE Data Hold from WE
Going High Going High
Address Setup to WE
Going High High High
Address Hold from WE CE Hold from WE
High
tWPH WE
Pulse Width High
Duration of Programming Operation Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) Write Recovery before Read VPP Hold from Valid SRD RP VHH Hold from Valid SRD Boot-Block Relock Delay
PROM Programmer Specifications
Versions Symbol tGHHWL tWHGH OE OE Parameter VHH Setup to WE VHH Hold from WE Going Low High VCC g10% Notes 28 28 28F001BX-120 Min 480 480 Max 28F001BX-150 Min 480 480 Max Unit ns ns
NOTES 1 Read timing characteristics during erase and program operations are the same as during read-only operations Refer to AC Characteristics for Read-Only Operations 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte programming or block erasure 4 Refer to Table 3 for valid DIN for byte programming or block erasure 5 The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel Flash Memory including byte program and verify (programming) and block precondition precondition verify erase and erase verify (erasing) 6 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of program erase success (SR 3 4 5 e 0) 7 For boot block programming and erasure RP should be held at VHH until determination of program erase success (SR 3 4 5 e 0) 8 Alternate boot block access method 9 Erase Program Cycles on extended temperature products is 10 000 cycles 10 See standard test configuration
24
28F001BX-T 28F001BX-B
ERASE AND PROGRAMMING PERFORMANCE
Parameter Boot Block Erase Time Boot Block Program Time Parameter Block Erase Time Parameter Block Program Time Main Block Erase Time Main Block Program Time Chip Erase Time Chip Program Time
NOTES 1 25 C 12 0 VPP 2 Excludes System-Level Overhead
Notes 2 2 2 2 2 2 2 2
28F001BX-120 Min Typ(1) 2 10 0 15 2 10 0 07 3 80 2 10 10 10 2 39 Max 14 9 0 52 14 6 0 26 20 9 7 34 65 8 38 Min
28F001BX-150 Typ(1) 2 10 0 15 2 10 0 07 3 80 2 10 10 10 2 39 Max 14 9 0 52 14 6 0 26 20 9 7 34 65 8 38
Unit Sec Sec Sec Sec Sec Sec Sec Sec
25
28F001BX-T 28F001BX-B
290406 - 19
290406 - 20
Figure 13 28F001BX Typical Programming Capability
Figure 14 28F001BX Typical Programming Time at 12V
290406 - 21
290406 - 22
Figure 15 28F001BX Typical Erase Capability 26
Figure 16 28F001BX Typical Erase Time at 12V
28F001BX-T 28F001BX-B
Figure 17 AC Waveform for Write Operations 27
290406- 13
28F001BX-T 28F001BX-B
290406 - 15
Figure 18 Alternate Boot Block Access Method Using OE
28
28F001BX-T 28F001BX-B
AC CHARACTERISTICS FOR CE -CONTROLLED WRITES(1)
28F001BX-70 VCC e 5V Symbol Parameter Notes
g5%(8)
28F001BX-90 VCC e 5V
g10%(9)
VCC e 5V
g10%(9)
Units
30 pF Min tAVAV tPHEL tWLEL tELEH tWC tPS tWS tCP Write Cycle Time RP High Recovery to CE Going Low WE CE Setup to CE Pulse Width Going 2 2 3 4 Going Low 2 70 480 0 50 100 100 35 35 10 10 0 20 56 56 56 56 15 13 13 30 0 25 26 2 0 0 100 Max
100 pF Min 75 480 0 55 100 100 40 40 10 10 0 20 15 13 13 30 0 0 0 100 Max
100 pF Min 90 480 0 55 100 100 40 40 10 10 0 20 15 13 13 30 0 0 0 100 Max ns ns ns ns ns ns ns ns ns ns ns ns ms sec sec sec ms ns ns ns
tPHHEH tPHS RP VHH Setup to CE High tVPEH tAVEH tDVEH tEHDX tEHAX tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tEHGL tQVVL tQVPH tPHBR tVPS VPP Setup to CE tAS tDS tDH tAH
Going High Going
Address Setup to CE High Data Setup to CE Data Hold from CE
Going High High High
Address Hold from CE Hold from CE
tEHWH tWH WE tEPH CE
High
Pulse Width High
Duration of Programming Operation Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) Write Recovery before Read tVPH VPP Hold from Valid SRD tPHH RP VHH Hold from Valid SRD Boot-Block Relock Delay
NOTES 1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE defines the write pulse width (within a longer WE timing waveform) all set-up hold and inactive WE times should be measured relative to the CE waveform 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte programming or block erasure 4 Refer to Table 3 for valid DIN for byte programming or block erasure 5 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of program erase success (SR 3 4 5 e 0) 6 For boot block programming and erasure RP should be held at VHH until determination of program erase success (SR 3 4 5 e 0) 7 Alternate boot block access method 8 See high speed test configuration 9 See standard text configuration
29
28F001BX-T 28F001BX-B
AC CHARACTERISTICS FOR CE -CONTROLLED WRITES(1)
Versions Symbol tAVAV tPHEL tWLEL tELEH tPHHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tEHGL tQVVL tQVPH tPHBR tWC tPS tWS tCP Parameter Write Cycle Time RP WE CE High Recovery to CE Setup to CE Pulse Width VHH Setup to CE Going High 2 2 3 4 Going Low 2 VCC g10% Notes 28F001BX-120 Min 120 480 0 70 100 100 50 50 10 15 0 25 56 56 56 56 15 13 13 30 0 25 26 2 0 0 100 Max 28F001BX-150 Min 150 480 0 70 100 100 50 50 10 15 0 25 15 13 13 30 0 0 0 100 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ms sec sec sec ms ns ns ns
Going Low
tPHS RP tAS tDS tDH tAH tWH
tVPS VPP Setup to CE Data Setup to CE Data Hold from CE
Going High Going High
Address Setup to CE
Going High High High
Address Hold from CE WE Hold from CE
High
tEPH CE
Pulse Width High
Duration of Programming Operation Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) Write Recovery before Read tVPH VPP Hold from Valid SRD tPHH RP VHH Hold from Valid SRD Boot-Block Relock Delay
PROM Programmer Specifications
Versions Symbol tGHHEL tEHGH OE OE Parameter VHH Setup to CE VHH Hold from CE Going Low High VCC g10% Notes 27 27 28F001BX-120 Min 480 480 Max 28F001BX-150 Min 480 480 Max Unit ns ns
NOTES 1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE In systems where CE defines the write pulse width (within a longer WE timing waveform) all set-up hold and inactive WE times should be measured relative to the CE waveform 2 Sampled not 100% tested 3 Refer to Table 3 for valid AIN for byte programming or block erasure 4 Refer to Table 3 for valid DIN for byte programming or block erasure 5 Program and erase durations are measured to completion (SR 7 e 1) VPP should be held at VPPH until determination of program erase success (SR 3 4 5 e 0) 6 For boot block programming and erasure RP should be held at VHH until determination of program erase success (SR 3 4 5 e 0) 7 Alternate boot block access method
30
28F001BX-T 28F001BX-B
Figure 19 Alternate AC Waveform for Write Operations 31
290406- 16
28F001BX-T 28F001BX-B
ORDERING INFORMATION
290406 - 18
VALID COMBINATIONS 32-Lead TSOP Commercial E28F001BX-T70 E28F001BX-T90 E28F001BX-T120 E28F001BX-T150 E28F001BX-B70 E28F001BX-B90 E28F001BX-B120 E28F001BX-B150 Extended TE28F001BX-T90 TE28F001BX-T150 TE28F001BX-B90 TE28F001BX-B150 32-Lead PLCC N28F001BX-T70 N28F001BX-T90 N28F001BX-T120 N28F001BX-T150 N28F001BX-B70 N28F001BX-B90 N28F001BX-B120 N28F001BX-B150 TN28F001BX-T90 TN28F001BX-T150 TN28F001BX-B90 TN28F001BX-B150 32-Pin PDIP P28F001BX-T70 P28F001BX-T90 P28F001BX-T120 P28F001BX-T150 P28F001BX-B70 P28F001BX-B90 P28F001BX-B120 P28F001BX-B150 TP28F001BX-T90 TP28F001BX-B90
ADDITIONAL INFORMATION References
Order Number 292046 292077 292161 292178 294005 AP-316 AP-341 AP-608 AP-623 ER-20 Document ``Using Flash Memory for In-System Reprogrammable Nonvolatile Storage'' ``Designing an Updateable BIOS Using Flash Memory'' ``Implementing a Plug and Play BIOS Using Intel's Boot Block Flash Memory'' ``Multi-Site Layout Planning Using Intel's Boot Block Flash Memory'' ``ETOX II Flash Memory Technology''
32
28F001BX-T 28F001BX-B
Revision History
Number -004 Removed Preliminary classification Latched address A16 in Figure 5 Updated Boot Block Program and Erase section ``If boot block program or erase is attempted while RP is at VIH either the Program Status or Erase Status bit will be set to ``1'' reflective of the operation being attempted and indicating boot block lock '' Updated Figure 11 28F001BX Erase Suspend Resume Flowchart Added DC Characteristics typical current values Combined VPP Standby current and VPP Read current into one VPP Standby current spec with two test conditions (DC Characteristics table) Added maximum program erase times to Erase and Programming Performance table Added Figures 13-16 Added Extended Temperature proliferations -005 -006 -007 PWD changed to RP for JEDEC standardization compatibility Revised symbols i e CE OE etc to CE OE etc Added specifications for -90 and -70 product versions Added VOH CMOS Specification Added reference to 28F001BN Description
33

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